JTAG Programming

The JTAG boundary scan process is well described elsewhere. This page tells you how to actually issue bit sequences to control a JTAG device.

Pins

Pin Direction Meaning Comment
TRST in Reset Should be taken low to reset a JTAG device. In addition, JTAG devices require 5 clocks in the RESET state before they can be programmed.
TCLK in Clock Rising edges latch the state of TDI and TMS into the JTAG chip. Falling edges are used by the JTAG device to change the state of TDO.
TMS in Test Mode Select. This pin controls the wandering of the TAP controller state machine. See below.
TDI in Test Data In. Supply data to this pin. This data is used to fill the internal shift registers during I_SHIFT and D_SHIFT states.
TDO out Test Data Out. Data comes back from this pin, changing on the falling edge of TCLK, during the I_SHIFT and D_SHIFT states.

States

The TAP controller runs through various states, controlled by the TMS and TCLK. During two of these states the TDI and TDO pins become active, giving us access to the internal shift registers. The IRSHIFT state gives us access to the instruction register, which is typically 3-16 bits long. These instructions select one of the other, "data", registers. The "data" shift registers are of various lengths; there is usually one called "bypass" which is only 1 bit long. All the "data" shift registers are clocked in the DRSHIFT state.

Default State Transitions

IEEE 1149.1 TAP State Name SVF TAP Name Next state if TMS==0 Next state if TMS==1 comments
Test-logic-Reset RESET IDLE RESET
  • performs physical reset
Run-Test/Idle IDLE IDLE DRSELECT
Select-DR-Scan DRSELECT DRCAPTURE IRSELECT
Capture-DR DRCAPTURE DRSHIFT DREXIT1
  • data is sampled into the shift register
Shift-DR DRSHIFT DRSHIFT DREXIT1
  • data is shifted into TDI on the first rising edge after entering this state
  • output appears on TDO at the first falling edge after entering this state
  • choice of shift-register is controlled by the current instruction
Pause-DR DRPAUSE DRPAUSE DREXIT2
Exit1-DR DREXIT1 DRPAUSE DRUPDATE
Exit2-DR DREXIT2 DRSHIFT DRUPDATE
Update-DR DRUPDATE IDLE DRSELECT
  • data is moved from the shift register into the output pin latch
Select-IR-Scan IRSELECT IRCAPTURE RESET
Capture-IR IRCAPTURE IRSHIFT IREXIT1
  • old instruction is latched into instruction-shift-register
Shift-IR IRSHIFT IRSHIFT IREXIT1
  • see DRSHIFT
  • always uses the instruction shift register
Pause-IR IRPAUSE IRPAUSE IREXIT2
Exit1-IR IREXIT1 IRPAUSE IRUPDATE
Exit2-IR IREXIT2 IRSHIFT IRUPDATE
Update-IR IRUPDATE IDLE DRSELECT
  • instruction is moved from shift register into instruction register (and decoded)

Typical Sequences

Assume a chip which has a 4 bit instruction register.

Reset, then instruction shift in.

TRST: 110000000000000000000000000000000000000000000000000000000000
TCLK: 010101010101010101010101010101010101010101010101010101010101
TMS:  111111111111001111000000000011110000000000000000000000000000
TDI:  ----------------------iiiiiiii------------------------------
TDO:  ----------------------IIIIIIII------------------------------
state:rrrrrrrrrrrrrddssSSCCHHHHHHHHEEUUddddddddddddddddddddddddddd
r: reset
d: idle
s: drselect
c: drcapture
h: drshift
u: drupdate
S: irselect
C: ircapture
H: irshift
E: irexit1
U: irupdate
i: instruction bits
I: previous instruction bits
a: data bits to set into the boundary pins
A: previous data bits

Instruction shift in, followed by data for the 10 boundary pins. The instruction is 0000.

TCLK: 01010101010101010101010101010101010101010101010101010101
TMS:  00000011110000000000111111000000000000000000000011110000
TDI:  --------------iiiiiiii--------aaaaaaaaaaaaaaaaaaaa------
TDO:  --------------IIIIIIII--------AAAAAAAAAAAAAAAAAAAA------
state:dddddddssSSCCHHHHHHHHEEUUsscchhhhhhhhhhhhhhhhhhhheeuudddd

Shorter form, without the clocks shown. 

TMS:  0001100000111000000000001100
TDI:  -------iiii----aaaaaaaaaa---
TDO:  -------IIII----AAAAAAAAAA---
state:dddsSCHHHHEUschhhhhhhhhheudd

untested